1. Field of the Invention
The present invention relates to an integrated semiconductor circuit. More specifically, the invention relates to means for providing back-bias for P-channel type transistor in a boost circuit.
2. Description of the Related Art
Conventionally, semiconductor memories and so forth of integrated semiconductor circuits and so forth employ a boost circuit for producing a voltage higher than potential voltage for the purpose of signal wave shaping and so forth. The boost circuit is also employed in a substrate potential generating circuit, active pull-up circuit and so on.
FIG. 3 shows one typical example of the boost circuit.
The boost circuit 5 includes a N-channel type transistor 1 having the drain and the gate connected to a high potential power source, such as Vcc, and a P-channel type transistor 2 having the source connected to the source of the N-channel type transistor 1, the drain d connected to an output 4, and the gate connected to an input signal source. The node section N between of the N-channel type transistor 1 and the P-channel type transistor 2 is connected to the output of a boost signal generating means 3.
In boost circuit 5, the P-channel type transistor 2 serves as a driver.
In the prior art, as shown in FIG. 3, the back gate BG of the P-channel type transistor is connected to the node section N so that the back gate bias becomes equal to the drain voltage of the N-channel type transistor and thus the P-channel type transistor is prevented from falling into a positive bias state to thereby cause a malfunction.
The boost signal generating means 3 generally comprises an appropriate oscillation means or a buffer means 6 and an appropriate capacitative means 7 to generate a pulse form output as the boost signal. The boost signal thus generated is applied to the node section N to activate the P-channel type transistor 2 to set the potential of the output or a substrate 4 at a higher level than the potential power source, such as Vcc.
However, in the conventional boost circuit 5, the potential b at the node section N is initially maintained to be lower than Vcc for the corresponding magnitude to the threshold level Vth of the N-channel type transistor 2, i.e. Vcc-Vth, as shown in FIG. 4. The charge at the node section N by the boost signal has to charge the N well capacity of the P-channel type transistor. As a result, the rising gradient of the potential b at the node section N by the boost signal becomes relatively moderate so that, when the boost signal a is generated after switching the input signal level from "H" level to "L" level, an increase in the potential b at the node section N can be substantially delayed. Therefore, the timing to raise the potential d of the substrate 4 over Vcc can be delayed to slow-down the process speed of the integrated semiconductor circuit per se.